1. Field of the Invention
The present invention relates to a clock recovery arrangement which is especially suitable for an information transmission system using the time-division multiple-access (TDMA) principle in one transmission direction. The system a central station and remote stations, each station having at least one transmitter circuit and one receiver circuit. Information sent by the transmitter circuit of the central station to the receiver circuit of the remote stations is time-division multiplexed and synchronized by means of a phase-locked loop producing at least a multiplex clock signal. Information sent by the transmitter circuits of the remote stations is transmitted to the receiver circuit of the central station in accordance with the TDMA principle and is synchronized by the clock recovery arrangement. The clock recovery arrangement includes at least a phase comparator, a programmable frequency divider, an oscillator applying a reference signal to the programmable frequency divider.
2. Prior Art
Such clock recovery arrangements are well-known, particularly the arrangement described in U.S. Pat. No. 3,983,498. In that patent the clock recovery arrangement uses the output signal of a non-controlled oscillator as a reference signal. This output signal is divided by means of programmable divider and thereafter compared by means of a phase comparator to the signal conveying the binary information components at a rate of 24 kbit/s. The output of the phase comparator is fed back to a control input of the programmable divider in order to modify the division performed by the divider and thus leads to synchronization of the input information components.
A first disadvantage of such an arrangement using a non-controlled oscillator is that at its output a residual jitter remains. The jitter makes it impossible to handle the information components effectively and with precision. This difficulty is greater when the transmission rate amounts to some Mbit/s.
A second disadvantage of such an arrangement is that the phase comparator whose output is not "smoothed" results in too coarse a quantization of the programmable divider to obtain fast and accurate synchronization.